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| AT91EB42 Evaluation Board ............................................................................. User Guide Table of Contents Section 1 Overview............................................................................................... 1-1 1.1 1.2 1.3 Scope........................................................................................................1-1 Deliverables ..............................................................................................1-1 The AT91EB42 Evaluation Board .............................................................1-1 Section 2 Setting Up the AT91EB42 Evaluation Board .................................................................................. 2-1 2.1 2.2 2.3 2.4 2.5 2.6 2.7 Electrostatic Warning ................................................................................2-1 Requirements............................................................................................2-1 Layout .......................................................................................................2-1 Jumper Settings ........................................................................................2-2 Powering Up the Board.............................................................................2-2 Measuring Current Consumption on the AT91M42800 ............................2-2 Testing the AT91EB42 Evaluation Board .................................................2-2 Section 3 The On-board Software ........................................................................ 3-1 3.1 3.2 3.3 3.4 3.5 3.6 AT91EB42 Evaluation Board ....................................................................3-1 Boot Software Program.............................................................................3-1 Programmed Default Memory Mapping ....................................................3-2 SRAM Downloader ...................................................................................3-2 Angel Monitor ............................................................................................3-2 Programmed Default Speed .....................................................................3-2 Section 4 Circuit Description................................................................................. 4-1 4.1 4.2 AT91M42800 Processor ...........................................................................4-1 Expansion Connectors and JTAG Interface..............................................4-1 I/O Expansion Connector ...................................................................4-1 EBI Expansion Connector ..................................................................4-1 JTAG Interface ...................................................................................4-1 4.2.1 4.2.2 4.2.3 4.3 4.4 4.5 4.6 4.7 Memories ..................................................................................................4-2 Analog-to-digital Converter .......................................................................4-2 Power and Crystal Quartz .........................................................................4-2 Push Buttons, LEDs, Reset and Serial Interfaces ....................................4-2 Layout Drawing .........................................................................................4-3 i Table of Contents Section 5 Appendix A - Configuration Straps....................................................... 5-1 5.1 5.2 5.3 5.4 Configuration Straps (CB1 - 23, JP1 - 8) ..................................................5-1 Power Consumption Measurement Strap (JP5) .......................................5-4 Ground Links (JP6) ...................................................................................5-4 Increasing Memory Size ...........................................................................5-4 Section 6 Appendix B - Schematics..................................................................... 6-1 6.1 Schematics ...............................................................................................6-1 ii Section 1 Overview 1.1 Scope The AT91EB42 Evaluation Board enables real-time code development and evaluation. It supports the AT91M42800. This guide focuses on the AT91EB42 Evaluation Board as an evaluation and demonstration platform: Section 1 provides an overview. 1.2 Deliverables 1.3 The AT91EB42 The board consists of an AT91M42800 together with several peripherals: Two serial ports Evaluation Board AT91EB42 Evaluation Board User Guide Section 2 describes how to set up the evaluation board. Section 3 details the on-board software. Section 4 contains a description of the circuit board. Section 5 and Section 6 are two appendices covering configuration straps and schematics, including pin connectors. The evaluation board is delivered with a DB9 plug-to-DB9 socket straight-through serial cable to connect the target evaluation board to a PC. A bare power lead with a 2.1 mm jack on one end for connection to a bench power supply is also delivered. The evaluation board is also delivered with a CD-ROM that contains an evaluation version of the software development toolkit and the documentation that outlines the AT91 microcontroller family. The evaluation board is capable of supporting different kinds of debugging systems, using an ICE interface or the on-board Angel Debug Monitor. Refer to the AT91EB42 Getting Started Tutorial documents for recommendations on using the evaluation board in a full debug environment. Reset push button Four user-defined push buttons Eight LEDs a 256 KB 16-bit SRAM (upgradeable to 1M byte) a 2 MB 16-bit Flash (of which 1M byte is available for user software) a 4 MB Serial Data Flash a 64 KB Serial EEPROM a 32 KB SPI EEPROM 1-1 Overview 2 x 32-pin EBI expansion connectors 2 x 32-pin I/O expansion connectors 20-pin JTAG interface connector If required, user-defined peripherals can also be added to the board. See Section 5 for details. Figure 1-1. AT91EB42 Evaluation Board Block Diagram AT91M42800 Reset Controller 8K Byte RAM ARM7TDMI Processor EBI SRAM EBI Expansion Connector Flash JTAG ICE Connector 32.768 KHz Crystal Push-buttons Reset Controller 2.1mm DC Power Socket Power Supply Fast-charge Controller Battery Connector 1-2 ASB Clock Generator AMBA Bridge Serial EEPROM PIO LEDs Interrupt Controller APB System Timer Watchdog Timer Counters Serial Data Flash SPI Serial EEPROM I/O Expansion Connector Reset PIO Serial Ports RS232 Transceivers DB9 Serial Connectors AT91EB42 Evaluation Board User Guide Section 2 Setting Up the AT91EB42 Evaluation Board 2.1 Electrostatic Warning The AT91EB42 Evaluation Board is shipped in protective anti-static packaging. The board must not be subjected to high electrostatic potentials. A grounding strap or similar protective device should be worn when handling the board. Avoid touching the component pins or any other metallic element. Requirements in order to set up the AT91EB42 Evaluation Board are: The AT91EB42 Evaluation Board itself 2.2 Requirements 2.3 Layout AT91EB42 Evaluation Board User Guide The DC power supply capable of supplying 7.5V to 9V at 1A (not supplied) Figure 2-1 shows the layout of the AT91EB42 Evaluation Board. Figure 2-1. Layout of the AT91EB42 Evaluation Board 2-1 Setting Up the AT91EB42 Evaluation Board 2.4 Jumper Settings JP1 is used to boot standard or user programs. For standard operations, set it in the STD position. JP8 is used to select the core power supply of the AT91M42800: 3.3V or 1.8V. For operation at 1.8V, MCK frequency shall be limited to 17 MHz. For more information about jumpers and other straps, see Section 5. 2.5 Powering Up the Board DC power is supplied to the board via the 2.1 mm socket (J1) shown in Figure 2-2. The polarity of the power supply is not critical. The minimum voltage required is 7V. Figure 2-2. 2.1 mm Socket positive (+) or negative (-) 2.1 mm connector A battery power supply can be connected to the board via the J3 connector. A battery fast-charge controller is provided on-board to charge this battery. The board has a voltage regulator providing +3.3V. The regulator allows the input voltage to range from 7V to 9V. When you switch the power on, the red LED marked POWER lights up. If it does not, switch off and check the power supply connections. 2.6 Measuring Current Consumption on the AT91M42800 The board is designed to generate the power for the AT91 product, and only the AT91 product, through the jumper JP5 (VDDIO) and JP8 (VDDCORE). This feature enables measurements to be made of the current consumption of the AT91 product. See Section 5 for further details. 2.7 Testing the To test the AT91EB42 Evaluation Board, perform the following steps: AT91EB42 1. Hold down the SW1 button and power-up the board, or generate a reset and wait for the light sequence on each LED to complete. All the LEDs light once and the Evaluation Board LED D1 remains lit. 2. Release the SW1 button. The LEDs D1 to D7 light up one after the other. If any of the LEDs lights up twice, there is an error. The LEDs represent the following components: D1 for the internal RAM If a test is not carried out, the corresponding LED remains unlit and the test sequence restarts. 2-2 D2 for the external RAM D3 for the external Flash D4 for the serial EEPROM D5 for the SPI DataFlash(R) D6 for the EEPROM D7 for the USART D8 is reserved AT91EB42 Evaluation Board User Guide Section 3 The On-board Software 3.1 AT91EB42 The AT91EB42 Evaluation Board embeds an AT49BV1604 Flash memory device proEvaluation Board grammed with default software. Only the lowest 8 x 8 KB sectors are used. The remaining sectors are user definable, and can be programmed using one of the Flash downloader solutions offered in the AT91 library. When delivered, the Flash memory device contains: the boot program The boot program, functional test software (FTS) and SRAM downloader are in sector 0 of the Flash. This sector is locked to prevent accidental erase, but it can be unlocked by applying 12V to the RESET pin. 3.2 Boot Software Program AT91EB42 Evaluation Board User Guide the functional test software the SRAM downloader the Angel Debug Monitor a default user boot with a default application The boot software program configures the AT91M42800, and thus controls the memory and other board components. The boot software program is started at reset if JP1 is in the STD position. If JP1 is in the USER position, the AT91M42800 boots from address 0x01010000 in the Flash, which must have a user-defined boot. The boot software program first initializes the EBI, then executes the REMAP procedure, and then checks the state of the buttons. When the button SW1 is pressed: All the LEDs light up together. The D1 LED remains lit until SW1 is released. The functional test software (FTS) is started. When the button SW2 is pressed: All the LEDs light up together. The D2 LED remains lit until SW2 is released. The SRAM downloader is activated. When SW3 or SW4 are pressed or no buttons are pressed: Branch at address 0x0100 2000. The Angel Debug Monitor starts from this address by recopying itself in external SRAM. 3-1 The On-board Software 3.3 Programmed Default Memory Mapping Table 3-1 defines the mapping defined by the boot program. Table 3-1. Memory Map Part Name U1 U2-U3 Start Address 0x01000000 0x02000000 End Address 0x011FFFFF 0x02040000 Size 2M Bytes 256K Bytes Device Flash AT49BV1604 SRAM The boot software program, FTS and SRAM downloader are in sectors 1 and 2 of the Flash device. Sectors 2 to 8 support the Angel Debug Monitor. Sector 24 at address 0x0110 0000 must be programmed with a boot sequence to be debugged. This sector can be mapped at address 0x0100 0000 (or 0x0 after a reset) when the jumper JP1 is in the USER position. 3.4 SRAM Downloader The SRAM downloader allows an application to be loaded in the SRAM at the address 0x02000000, then activated. It is started by the boot if the SW2 button is pressed at reset. The procedure is as follows: 1. Connect the AT91EB42 Evaluation Board to the host PC serial "A" connection using the straight serial cable provided. 2. Power-on or press "RESET", holding down the SW2 button at the same time. Wait for D2 to light up and then release SW2. 3. Start the BINCOM utility, available in the AT91 library, on the host computer: Select the port for communications (COM1 or COM2, depending on where you connected the serial cable on the host PC) and the baud rate for communications (115200 bds, 1 stop bit, no parity). Open the file to be downloaded and send it. Wait for the end of the transfer. 4. Press any button to end the download. The control is switched to the address 0x02000000. 3.5 Angel Monitor The Angel monitor is located in the Flash from 0x01002000 up to 0x0100FFFF. The boot program starts it if no button is pressed at reset. When Angel starts, it recopies itself in SRAM in order to run faster. The SRAM used by Angel is from 0x02020000 to 0x02040000, i.e., the highest half part of the SRAM. The Angel on the AT91EB42 Evaluation Board can be upgraded regardless of the version programmed on it. Note that if the debugger is started through ICE while the Angel monitor is on, the Advanced Interrupt Controller (AIC) and the USART channel are enabled. 3.6 Programmed Default Speed As the speed of the AT91M42800 is programmable, the boot software program initializes the device to run as fast as possible, i.e., at 40 MHz. The boot software program and the functional test software are run at this speed. The SRAM downloader, after initialization of the USARTs, enters the processor in idle mode and activates the downloaded application at this speed. When Angel is started, it also runs at 40 MHz and the user should not modify this frequency without reprogramming the speed of the USARTs. 3-2 AT91EB42 Evaluation Board User Guide Section 4 Circuit Description 4.1 AT91M42800 Processor Figure 6-1 on page 6-2 shows the AT91M42800. The footprint is for a 144-pin TQFP package. Strap CB20 enables the user to choose between the standard ICE debug mode and the JTAG boundary scan mode of operation. The operating mode is defined by the state of the JTAGSEL input detected at reset. Jumper JP5 (see Figure 6-8 on page 6-9 in Section 6, "Appendix B - Schematics") can be removed by the user to allow measurement of the current demand by the whole microcontroller (VDDIO and VDDCORE). Jumper JP8 can be removed to measure the core microcontroller consumption (VDDCORE). 4.2 Expansion Connectors and JTAG Interface The two expansion connectors, I/O expansion connector and EBI expansion connector, and the JTAG interface are described below. The I/O and EBI expansion connectors' pinout and position are compatible with the other evaluation boards (except the I/O expansion connector pinout and position of the EB40) so that users can connect their prototype daughter boards to any of these evaluation boards. The I/O expansion connector makes the general-purpose I/O (GPIO) lines, VCC3V3 and Ground, available to the user. Configuration straps CB2, CB3, CB4, CB11, CB13, CB14, CB15, CB17, CB18 and CB19 are used to select between the I/O lines being used by the evaluation board or by the user via the I/O expansion connector. The connector is not fitted at the factory; however, the user can fit any 32 x 2 connector on a 0.1" (2.54 mm) pitch. The schematic (Figure 6-4 on page 6-5 in Section 6, "Appendix B - Schematics") also shows the bus expansion connector which, like the I/O expansion connector, is not fitted at the factory. The user can fit any 32 x 2 connector on a 0.1" (2.54 mm) pitch to gain access to the data, address, chip select, read/write, oscillator output and wait request pins. VCC3V3 and ground are also available on this connector. Configuration strap CB1, when open, allows the user to connect the EBI expansion connector to the MPI expansion connector of an AT91EB63 evaluation board without any conflicts. 4.2.1 I/O Expansion Connector 4.2.2 EBI Expansion Connector 4.2.3 JTAG Interface An ARM(R)-standard 20-pin box header (P5) is provided to enable connection of an ICE interface to the JTAG inputs on the AT91. This allows code to be developed on the board without using system resources such as memory and serial ports. AT91EB42 Evaluation Board User Guide 4-1 Circuit Description 4.3 Memories The schematic (Figure 6-3 on page 6-4 in Section 6, "Appendix B - Schematics") shows one AT49BV1604 2 MB 16-bit Flash, one AT45DB321 4 MB serial DataFlash, one AT24C512 64 KB EEPROM, one AT25256 32 KB EEPROM and two 128K/512K x 8 SRAM devices. Note: The AT91EB42 is fitted with two 128K x 8 SRAM devices. A footprint is provided for the user to fit a multi-chip device memory that embeds Flash (1 MB) and SRAM (128 KB) in a single component in place of the Flash and SRAM devices (U7: M36W108AB from ST). Strap JP1 shown on the schematic is used to select the part of 1 MB of the Flash to be accessed. This is to enable users to Flash download their application in the second part of the Flash and to boot on it. 4.4 Analog-to-digital Converter A footprint is provided for the user to fit a 4-channel 10-bit ADC device (AD7817ARU from Analog Devices; see Figure 6-10 on page 6-11 in Section 6, "Appendix B - Schematics"). This device is interfaced to the AT91 microcontroller via the SPIA peripheral. The voltage reference used is the 2.5V on-chip. This device embeds a temperature sensor and is placed near the 32.768 KHz crystal quartz. Thus the user is able to take into account the frequency drift due to temperature evolution by a software program. By default, two of the ADC channels are dedicated to supervise the board power supply voltage levels (channel 1 for the battery power supply, channel 2 for the standard power supply). 4.5 Power and Crystal Quartz The AT91M42800 master clock is derived from a 32.768 KHz crystal quartz. The onchip low-power oscillator together with two PLL-based frequency multipliers and the prescaler results in a programmable master clock between 500 Hz and 33 MHz. Two sets of components for the PLL filters are fitted by default on the board (Figure 6-6 on page 6-7 in Section 6, "Appendix B - Schematics"). They are calculated to provide a 16.77 MHz (PLLA: multiplier factor of 512 and settling time of 600=s) or a 33.55 MHz (PLLB: multiplier factor of 1024 and settling time of 4 ms) master clock frequency. The voltage regulator provides 3.3V to the board and will light the red POWER LED (D11) when operating. Power can be applied via the 2.1 mm connector to the regulator in either polarity because of the diode-rectifying circuit. Another regulator allows the user to power the AT91M42800 core with 3.3V or 1.8V by means of the JP8 jumper. A battery power supply can be applied via the J3 connector. The type of battery and connections to be used are shown in the schematics (Figure 6-9 on page 6-10 in Section 6, "Appendix B - Schematics"). This type of battery will ensure the power supply of the board for approximately 30 minutes. A battery fast-charge controller is provided onboard to charge this battery. The number of series cells to be charged is set to 5, but can be changed via the CB21, CB22 and CB32 configuration straps. The maximum time allowed for fast-charging is set to 264 minutes. 4.6 Push Buttons, LEDs, Reset and Serial Interfaces The IRQ0, TIOA0, PB6 and PB21 switches are debounced and buffered. A supervisory circuit has been included in the design to detect and consequently reset the board when the 3.3V supply voltage drops below 3.0V. Note that this voltage can be changed depending on the board production series. The supervisory circuit also provides a debounced reset signal. This device can also generate the reset signal in case 4-2 AT91EB42 Evaluation Board User Guide Circuit Description of watchdog time-out as the pin NWDOVF of the AT91M42800 is connected to its input MR. The assertion of this reset signal will light up the red RESET LED (D10). By pressing the CLEAR RESET push button (S1), the LED can be turned off. Another supervisory circuit initializes separately the microcontroller-embedded JTAG/ICE interface when the 3.3V supply voltage drops below 3.0V. Note that this voltage can be changed, depending on the board production series. These separated reset lines allow the user to reset the board without resetting the JTAG/ICE interface while debugging. The schematic (Figure 6-5 on page 6-6 in Section 6, "Appendix B - Schematics") also shows eight general-purpose LEDs connected to port B PIO pins (PB8 to PB15). Two 9-way D-type connectors (P3/4) are provided for serial port connection. Serial port A (P3) is used primarily for host PC communication and is a DB9 female connector. TXD and RXD are swapped so that a straight-through cable can be used. CTS and RTS are connected together, as are DCD, DSR and DTR. Serial port B (P4) is a DB9 male connector with TXD and RXD obeying the standard RS-232 pinout. Apart from TXD, RXD and ground, the other pins are not connected. LEDs are connected to the TX and RX signals of both serial ports and show activity on these serial links. A MAX3223 device (U10) and associated bulk storage capacitors provide RS-232 level conversion. 4.7 Layout Drawing The layout diagram (Figure 6-1 on page 6-2 in Section 6, "Appendix B - Schematics") shows an approximate floorplan for the board. This has been designed to give the lowest board area, while still providing access to all test points, jumpers and switches on the board. The board is provided with four mounting holes, one at each corner, into which feet are attached. The board has two signal layers and two power planes. AT91EB42 Evaluation Board User Guide 4-3 Circuit Description 4-4 AT91EB42 Evaluation Board User Guide Section 5 Appendix A - Configuration Straps 5.1 Configuration Straps (CB1 - 23, JP1 - 8) By adding the I/O and EBI expansion connectors, users can connect their own peripherals to the evaluation board. These peripherals may require more I/O lines than available while the board is in its default state. Extra I/O lines can be made available by disabling some of the on-board peripherals or features. This is done using the configuration straps detailed below. Some of these straps present a default wire (notified by the default mention) that must be cut before soldering the strap. CB1 Closed Open (1) On-board PB5/A23/CS4 Signal AT91 PB5/A23/CS4 signal is connected to the EBI expansion connector (P1-B21). AT91 PB5/A23/CS4 signal is not connected to the EBI expansion connector (P1-B21). This authorizes users to connect the EBI expansion connector of this board to the MPI expansion connector of an AT91EB63 Evaluation Board without conflict problems. CB2, CB3, CB4 Closed Open (1) ADC Enabling ADC (U20) control lines enabled ADC (U20) control lines disabled. This authorizes users to connect the corresponding PIO to their own resources via the I/O expansion connector. CB5 Closed(1) Battery Power Supply Supervisory Enabling Battery power supply is supervised by the ADC (U20) channel 1 via a resistor bridge. The ratio is set to 0.3333 so that the battery voltage range can be supervised (5.5V to 6.2V). Battery power supply is not connected to the ADC (U20) channel 1. This authorizes users to connect the corresponding ADC channel to their own resources via the I/O expansion connector. Open AT91EB42 Evaluation Board User Guide 5-1 Appendix A - Configuration Straps CB7 Closed (1) Standard Power Supply Supervisory Enabling Standard power supply is supervised by the ADC (U20) channel 2 via a resistor bridge. The ratio is set to 0.1485 so that the standard power supply can be supervised up to 15V. Standard power supply is not connected to the ADC (U20) channel 2. This authorizes users to connect the corresponding ADC channel to their own resources via the I/O expansion connector. Open CB6, CB8 Closed Open (1) ADC Channels 3 and 4 Enabling ADC (U20) channels 3 and 4 are connected to ground. ADC (U20) channels 3 and 4 are not connected to ground. This authorizes users to connect the corresponding ADC channel to their own resources via the I/O expansion connector. CB9 Closed (1) Open On-board Boot Chip Select AT91 NCS0 select signal is connected to the Flash memory. AT91 NCS0 select signal is not connected to the Flash memory. This authorizes users to connect the corresponding select signal to their own resources via the EBI expansion connector. CB10 Closed Open (1) Flash Reset The on-board reset signal is connected to the Flash NRESET input. The on-board reset signal is not connected to the Flash NRESET input. CB11 Closed(1) Open PB22 Ready/Busy MCM Memory Signal AT91 PB22 signal is connected to the multi-chip device memory (U7), Ready/Busy output pin AT91 PB22 signal is not connected to the multi-chip device memory (U7), Ready/Busy output pin. This authorizes users to connect the corresponding signal to their own resources via the I/O expansion connector CB12 Open Closed(1) Boot Mode Strap Configuration BMS AT91 input pin is set for the microcontroller to boot on an external 16-bit memory at reset. BMS AT91 input pin is set for the microcontroller to boot on an external 8-bit memory at reset. I2C EEPROM Enabling EEPROM communication enabled EEPROM communication disabled. This authorizes users to connect the corresponding PIO to their own resources via the I/O expansion connector. CB13, CB14 Closed(1) Open 5-2 AT91EB42 Evaluation Board User Guide Appendix A - Configuration Straps CB15 Closed(1) Open Serial DataFlash Enabling AT91 NPCSA0 select signal is connected to the serial DataFlash memory. AT91 NPCSA0 select signal is not connected to the serial DataFlash memory. This authorizes users to connect the corresponding PIO to their own resources via the I/O expansion connector. CB17 Closed Open (1) SPI EEPROM Enabling EEPROM communication enabled EEPROM communication disabled. This authorizes users to connect the corresponding PIO to their own resources via the I/O expansion connector. CB18 Closed (1) PB20 ADC Write Access Signal AT91 PB20 signal is used to control the RD/WR ADC (U20) input pin. Prior to a write access, position this PIO line in a low state. Position it in a high state prior to a read access. AT91 PB20 signal is not used to control the RD/WR ADC (U20) input pin. This authorizes users to connect the corresponding signal to their own resources via the I/O expansion connector. Open CB19 Closed(1) Open PB18 End of Fast Charge Signal AT91 PB18 signal is connected to the battery charger (U16), NFASTCHG output pin. AT91 PB18 signal is not connected to the battery charger (U16), NFASTCHG output pin. This authorizes users to connect the corresponding signal to their own resources via the I/O expansion connector. CB20 1-2 2-3 (1) JTAGSEL AT91 standard ICE debug feature enabled IEEE 1149.1 JTAG boundary scan feature enabled CB21, CB22, CB23 Number of Cells 1 2 4 5 (1) Charger Device (U16): Programming the Battery Number of Cells CB21 Open Open Closed Open Open Closed CB22 Closed Open Open Closed Open Open CB23 Closed Closed Closed Open Open Open 6 8 AT91EB42 Evaluation Board User Guide 5-3 Appendix A - Configuration Straps JP1 2-3 1-2 User or Standard Boot Selection The first half part of the Flash memory is accessible at its base address. The second half part of the Flash memory is accessible at its base address. This authorizes users to download their own application software in this part and to boot on it. JP2 Open Closed Push Button Enabling SW1-4 inputs to the AT91 are valid. SW1-4 inputs to the AT91 are not valid. This authorizes users to connect the corresponding PIO to their own resources via the I/O expansion connector. JP3 Open Closed User or Standard Boot Selection The RS-232 transceivers are enabled. The RS-232 transceivers are disabled. This authorizes users to connect the corresponding PIO to their own resources via the I/O expansion connector. JP8 2-3 1-2 Note: Core Power Supply Selection The AT91 core is powered by 3.3V power supply. The AT91 core is powered by 1.8V power supply. In this case, the maximum frequency that can be used is 17 MHz. 1. Hardwired default position: To cancel this default configuration, cut the wire on the board. 5.2 Power Consumption Measurement Strap (JP5) The JP5 strap enables connection of an ammeter to measure the AT91M42800 global consumption (VDDCORE and VDDIO) when VDDCORE power supply is derived from VDDIO (JP8 in 3V3 position). Core consumption can be measured by connecting another ammeter between JP8 1-2 or 2-3, depending on the power supply used to power the core. The current measured on E11 is the total current required by the AT91M63200 on both VDDIO and VDDPLL. It is also the current consumed by the switching regulator VR1 that provides the 1.8V. 5.3 Ground Links (JP6) Increasing Memory Size The JP6 strap allows the user to connect the electrical and mechanical grounds. 5.4 The AT91EB42 Evaluation Board is supplied with two 128K x 8 byte SRAM memories. If, however, the user needs more than 256K bytes of memory, the devices can be replaced with two 512K x 8 3.3V 10/15 ns SRAMs, giving in total 1024K bytes. 5-4 AT91EB42 Evaluation Board User Guide Section 6 Appendix B - Schematics 6.1 Schematics The following schematics are appended: * Figure 6-1. PCB Layout * Figure 6-2. AT91EB42 Blocks Overview * Figure 6-3. EBI Memories * Figure 6-4. I/O and EBI Expansion Connectors * Figure 6-5. Push Buttons, LEDs and Serial Interface * Figure 6-6. AT91M42800 * Figure 6-7. Reset and JTAG Interface * Figure 6-8. Power Supply and Battery Charger * Figure 6-9. Battery Type and Connection * Figure 6-10. SPI Memories, I2C Memories and SPI ADC The pin connectors are indicated on the schematics: P1 = EBI Expansion Connector (Figure 6-4) P2 = I/O Expansion Connector (Figure 6-4) P3 = Serial A (Figure 6-5) P4 = Serial B (Figure 6-5) P5 = JTAG Interface (Figure 6-7) AT91EB42 Evaluation Board User Guide 6-1 Appendix B - Schematics Figure 6-1. PCB Layout 6-2 AT91EB42 Evaluation Board User Guide AT91EB42 Evaluation Board User Guide 6-3 Figure 6-2. AT91EB42 Blocks Overview EBI_[0..42] EBI_[0..42] IOB_32 IOB_52 EBI_[0..42] IOB_[0..57] IOB_16 IOB_15 IOB_14 IOB_13 IOB_12 IOB_11 IOB_3 IOB_49 IOB_50 IOB_46 IOB_47 EBI MEMORIES A20 PB22 EBI_41 NRST SERIAL MEMORIES IOB_[0..57] IOB_[54..57] VIN[1..4] NPCSA2 NPCSA1 NPCSA0 MOSIA MISOA SPCKA IRQ3 PB19 PB20 PB16 PB17 SERIAL MEMORIES memories connected on EBI MICROCONTROLLER IOB_[0..53] IOB_[0..53] IOB_[0..57] IOB_[0..57] INPUT / OUTPUT ON BOARD IOB_51 IOB_[36..45] PB21 PB[6..15] PA[6..7] PA[9..10] PA0 Serial Connectors / P.B. / LED EBI_[0..42] EBI_[0..42] IOB_[6..7] IOB_[9..10] IOB_0 micro / Rst / Wchdog / JTAG co. SUPPLY and RTC SAVE IOB_[0..57] PB18 IOB_48 EXTENSIONS CONNECTORS IOB_[0..57] EBI_[0..42] IOB_[0..57] EBI_[0..42] power supply / battery Extension Connectors Appendix B - Schematics 6-4 2Mbytes FLASH MEMORY U1 512k 128k 512k 128k 1Mbytes ( two 512kX8 ) SRAM with two footprints or 256kbytes ( two 128kX8 ) SRAM with two footprints. U2 U3 A18 A17 A16 A15 A14 A[0..19] D[0..15] A1 A2 A3 A4 A18 layout for SOJ 400mil. NRD NCS1 D8 D9 VCC3V3 D5 D4 D10 D11 NWR1 A5 A6 A7 A8 A19 VCC3V3 VCC3V3 VCC3V3 D7 D6 A1 A2 A3 A4 D15 D14 D13 D12 A13 A12 A11 A10 A9 A17 A16 A15 A14 NRD NCS1 D0 D1 VCC3V3 D2 D3 NWR0 A5 A6 A7 A8 A19 VCC3V3 A13 A12 A11 A10 A9 Figure 6-3. EBI Memories VCC3V3 Appendix B - Schematics I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 A0 A1 A2 A3 A4 CS D0 D1 VCC GND D2 D3 WE A5 A6 A7 A8 A9 NC A18 A17 A16 A15 OE D7 D6 GND VCC D5 D4 A14 A13 A12 A11 A10 NC A0 A1 A2 A3 A4 CS D0 D1 VCC GND D2 D3 WE A5 A6 A7 A8 A9 NC A18 A17 A16 A15 OE D7 D6 GND VCC D5 D4 A14 A13 A12 A11 A10 NC 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20B 25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 15 IDT71V424S10Y IDT71V424S10Y VCC3V3 VCC3V3 VCC3V3 VCCQ VCC U4 512k 1 47 37 C1 100nF C2 100nF C3 100nF U5 512k R1 100k A18 CE WE OE RESET VCC3V3 GND GND D0 D1 D2 D3 NWR0 A5 A6 A7 A8 A19 A13 A12 A11 A10 A9 D5 D4 VCC3V3 D7 D6 VCC3V3 GND 46 27 NCS1 NRD C5 100nF A1 A2 A3 A4 A17 A16 A15 A14 128k 9 10 14 13 NC NC NC NC / Vpp C4 100nF CB9 A18 1 2 128k 2 NCS0 NWE NOE N C S 0 _ 1 26 11 28 layout for TSSOP 400mil. NCS1 D8 D9 D10 D11 NWR1 CB10 A1 A2 A3 A4 A17 A16 A15 A14 NRD D15 D14 D13 D12 VCC3V3 NRST 1 2 NRST_1 12 1 R2 100k AT49BV1604-90TC VCC3V3 2 A5 A6 A7 A8 A19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 NC NC A0 A1 A2 A3 A4 CS D0 D1 VCC GND D2 D3 WE A5 A6 A7 A8 A9 NC NC NC NC NC A18 A17 A16 A15 OE D7 D6 GND VCC D5 D4 A14 A13 A12 A11 A10 NC NC NC 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 NC NC A0 A1 A2 A3 A4 CS D0 D1 VCC GND D2 D3 WE A5 A6 A7 A8 A9 NC NC NC NC NC A18 A17 A16 A15 OE D7 D6 GND VCC D5 D4 A14 A13 A12 A11 A10 NC NC NC 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A13 A12 A11 A10 A9 IDT71424S10PH U7 IDT71424S10PH EBI_[0..42] VCC3V3 EBI_[36..42] EBI_[16..35] R72 100K CB11 Ready/busy 1 IOB_52 2 CTL[0..6] CTL0 NWR0 NWE DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 RNB G5 PB22 D4 C6 C5 E3 C4 B5 G2 B4 D0 D1 D2 D3 D4 D5 D6 D7 A[0..19] EBI_[0..15] CTL1 NWR1 NUB D[0..15] CTL2 CTL5 CTL4 A20 IOB_32 3 JP1 jumper_3P U6A 2 1 NRD NRST NCS0 CTL6 NCS1 NOE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 NE1S E2S VCC3V3 F2 NC NC NC NC NC NC NC NC NC VCCF VCCS C106 100nF B1 C105 100nF C2 D3 E1 E2 F1 F3 G1 H1 H3 D5 D6 E6 E5 F6 C3 E4 F5 B3 H6 A5 A3 H2 G3 A2 H5 H4 STD BOOT 2 A20B NCS1 VCC3V3 A6 G6 NRD NWR0 NG NW A17 A18 A19 NEF NRP M36W108AB VSS VSS B6 D1 A4 A1 1 3 1 USER BOOT 74LVC02AD A17 A18 A19 C1 B2 F4 AT91EB42 Evaluation Board User Guide NCS0_1 NRST_1 D2 G4 Appendix B - Schematics Figure 6-4. I/O and EBI Expansion Connectors AT91EB42 Evaluation Board User Guide 6-5 TP 33 TP 33 TP 33 C14 47nF TP 33 6-6 VCC3V3 2 PB[6..15] R4 100K VCC3V3 VCC3V3 PB[6..15] JP2 jumper_NO VCC3V3 U8 1 R5 100k VALBP R3 100K VALBP VALBP 1 Red LED 18 VCC3V3 100R VCC3V3 D3 VCC3V3 100R VCC3V3 D4 R9 R8 100R 16 14 12 D2 R7 D1 R6 100R EN SW1 PB9 U9 1 2 PB11 3 PA0 PB7 TIOA0 19 IRQ0 6 4 6 8 C10 47nF SW2 C11 47nF R42 100k PB8 2 R43 100k 74LV125D PB10 EN EN 9 7 5 GND SIGNAL VCC3V3 10 20 3 D8 D7 D6 R12 R13 R11 D5 R10 100R Appendix B - Schematics 4 5 10 9 8 PB6 PB13 11 PB21 PB21 PB14 PB15 VCC3V3 R45 100k R44 100k 17 15 TCLK5 7 C12 14 2 100nF C13 VCC3V3 VCC3V3 100nF SW4 C15 47nF 13 TCLK0 PB12 11 VCC3V3 13 12 VCC3V3 100R VCC3V3 100R VCC3V3 100R VCC3V3 VCC3V3 R14 100K 1 R15 100K 74LV244D SW3 Figure 6-5. Push Buttons, LEDs and Serial Interface VCC3V3 C16 VCC3V3 D29 ORANGE LED 100nF 18 19 2 C1+ VCC GND V+ C19 V7 3 C1C2+ C2T1IN T2IN R1OUT R2OUT EN FORCEON U10 R1IN R2IN INVALID FORCEOFF T1OUT T2OUT 17 8 16 9 11 20 C18 100nF 4 5 C22 100nF 6 13 12 15 10 1 14 R75 100R R76 100R C17 100nF D30 ORANGE LED VCC3V3 VCC3V3 P3 DCD0 DSR0 TX0 RTS0 RX0 CTS0 DTR0 100nF C20 22pF C21 22pF PA0 R16 100k PA7 PA6 PA9 PA7 PA10 VAL_RS232 RXD0 RXD1 TXD0 TXD1 R73 100R R74 100R PA0 1 6 2 7 3 8 4 9 5 Sub D 9b F Usart 0: SERIAL A PA[6..7] PA[6..7] C25 C23 22pF C24 22pF 10nF PA[9..10] PA[9..10] VCC3V3 P4 2 RX1 JP3 jumper_NO VALID RS232 on IOB D31 GREEN LED D32 GREEN LED MAX3223ECAP VCC3V3 TX1 C26 22pF C27 22pF 1 1 6 2 7 3 8 4 9 5 Sub D 9b M Usart 1: SERIAL B R17 100K AT91EB42 Evaluation Board User Guide VCC3V3 VCC3V3 2 BMS CB16 VCC3V3 1 100K VT R46 NWAIT CTL3 R48 PA27 VCC3V3 R41 100K 1 CB12 2 VCC3V3 Default boot Mode : 16 Bits PA[0..29] 100K C43 1 2 2 Y1 32,768kHz 2 C44 C29 100nF 111 109 110 VDDIO 122 123 XOUT PA29 PLLRCB PLLRCA PA28 PA27 PA26 JTAG[0..4] JTAG[0..4] Guard ring 1 VT XIN XOUT C28 100nF XIN 1 VDDPLL NWDOVF PB[0..23] JTAGSEL JTAG2 JTAG1 JTAG4 JTAG3 JTAG0 VDDCORE CTL5 CTL3 CTL2 CTL0 CTL1 CTL4 CTL6 PB0 PB1 VDDIO 141 142 135 136 137 138 139 140 134 130 131 124 125 126 127 128 129 VDDIO 132 133 VDDIO 120 121 143 144 C30 100nF PA26 GND GND VDDIO GND VDDIO GND VDDIO VDDCORE 106 PA25 108 107 PLLRCA JTAGSEL TMS TDI TDO TCK NTRST Figure 6-6. AT91M42800 CTL[0..6] 112 GND 113 XIN 114 XOUT 115 GND PLL filter A R18 R19 1K50 1% 100R 1% 1 2 1 2 1 1 C45 C46 10nF 10% 2 116 PLLRCA 117 VDDPLL 118 PLLRCB 119 VDDPLL PB0 / NCS2 PB1 / NCS3 NWDOVF PA27 / BMS VDDCORE VDDIO VDDCORE PA29 / HOLD NWAIT NOE / NRD NWE / NWR0 NUB / NWR1 NCS0 NCS1 NRST PA28 / HOLDA 1 2 GND GND PA25 / MCKO Guard ring A[0..19] 100nF 10% 2 AT91EB42 Evaluation Board User Guide A0 A1 A2 A3 A4 A5 A6 A7 A8 PA24 / NPCSB3 PA23 / NPCSB2 PA22 / NPCSB1 PA21 / NPCSB0 / NSSB PA20 / MOSIB PA19 / MISOB PA18 / SPCKB NLB / A0 A1 A2 A3 A4 A5 A6 A7 A8 3 4 5 6 7 8 9 10 11 PA24 PA23 PA22 PA21 PA20 PA19 PA18 PA17 VDDIO PLLRCB C47 105 104 103 102 101 100 99 98 97 96 U11 PA17 / NPCSA3 GND VDDIO PLL filter B R20 R21 680R 1% 120R 1% 1 2 1 2 1 1F 10% 100nF 10% 2 C48 2 1 VDDIO VDDIO GND A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 PA10 / RXD1 PA9 / TXD1 / NTRI PA8 / SCK1 PA7 / RXD0 GND VDDIO / / / / CS7 CS6 CS5 CS4 85 84 89 88 87 86 VDDIO GND A19 PB2 PB3 PB4 PB5 / / / / A20 A21 A22 A23 D0 D1 D2 D3 PB12 / PB11 / PB10 / PB9 / PB8 / PB7 / PB6 / PB21 / PB20 / PB19 / PB18 / PB17 / PB16 / PB15 / PB14 / PB13 / PA16 / NPCSA2 PA15 / NPCSA1 PA14 / NPCSA0 / NSSA PA13 / MOSIA PA12 / MISOA PA11 / SPCKA 95 94 93 92 91 90 PA16 PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 VDDIO A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 VDDIO A19 PB2 PB3 PB4 PB5 D0 D1 D2 D3 35 36 GND VDDIO GND VDDIO VDDCORE VDDIO TCLK2 TIOB1 TIOA1 TCLK1 TIOB0 TIOA0 TCLK0 GND GND D12 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 C50 38 37 49 48 61 60 59 58 57 56 55 54 53 47 46 45 44 43 42 41 40 39 52 51 50 100nF PB12 PB11 PB10 PB9 PB8 PB7 PB6 C49 100nF 31 32 33 34 26 27 28 29 30 24 25 14 15 16 17 18 19 20 21 22 23 12 13 AT91M42800 JTAGSEL NWDOVF CTL5 JTAGSEL NWDOVF NRST PB[0..23] PA6 / TXD0 PA5 / SCK0 PA4 / FIQ PA3 / IRQ3 PA2 / IRQ2 PA1 / IRQ1 PA0 / IRQ0 PB23 / TIOB5 PB22 / TIOA5 VDDIO VDDCORE GND GND 83 82 81 80 79 78 77 76 75 74 73 PB23 PB22 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PA[0..29] IOB_[0..29] TCLK5 TIOB4 TIOA4 TCLK4 TIOB3 TIOA3 TCLK3 TIOB2 TIOA2 PB[0..23] 72 71 C51 100nF IOB_[30..53] EBI_[0..42] 70 69 68 67 66 65 64 63 62 IOB_[0..53] VDDIO VDDCORE PB21 PB20 PB19 PB18 PB17 PB16 PB15 PB14 PB13 VDDIO VDDCORE VDDCORE EBI_[36..42] D15 VDDIO CTL[0..6] D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 VDDIO EBI_[16..35] A[0..19] PB[0..23] EBI_[0..15] D[0..15] Appendix B - Schematics 6-7 6-8 VCC3V3 U12 VCC3V3 5 6 R23 RSTLED 100R 7 14 74LVC74AD 9 8 4 3 2 1 S C1 1D R 5 6 74LVC02AD S1 B.P. C52 VCC3V3 C53 VCC3V3 U13 1 GND RST MAX6315US30D4-T MR 3 CTL5 NRST VCC 2 4 R25 100k 100nF 100nF R78 100K VCC3V3 1 Appendix B - Schematics NRST U6B 4 10 11 12 13 R24 100R 3V3 SUPPLY RESET D10 Red LED D11 Red LED Figure 6-7. Reset and JTAG Interface CLEAR RST LED NWDOVF PBRST CTL6 RESET VCC3V3 3 CB20 SW5 TP 33 IEEE JTAGSEL JTAGSEL 2 ICE C94 VCC3V3 VCC3V3 C71 G5 4 1 VCC NTRST TDI TMS TCK TCK 13 NRST 15 17 JTAG0 C78 10pF C79 10pF C80 10pF C81 10pF JTAG1 JTAG2 JTAG3 19 TDO NRST NC NC HE10 2x10 3 JTAG0 JTAG1 MAX6315US30D4-T JTAG2 JTAG3 11 JTAG4 9 7 5 3 R27 100k P5 VCC GND GND GND GND 2 4 6 8 10 G1 G2 G3 G4 G2 G1 C72 10nF G7 G6 C75 10nF 10nF C73 10nF 100nF U14 1 GND RST MR VCC 2 1 JTAG GND GND GND GND GND 12 14 16 18 20 G5 G6 G7 G8 G9 G4 G3 C74 10nF G8 C76 10nF G9 C82 10nF C77 10nF JTAG[0..4] C83 10nF C86 10nF JTAG4 C84 10pF C85 10pF AT91EB42 Evaluation Board User Guide NRST Vps D12 1 L1 VCC3V3 D24 BOOST VIN1F VIN SHTDN SYNC JP5 jumper_NO SENSE 7 2 10 H VSW 10MQ100N 5 C57B 10 F / 25V VC D15 1N5817 C58B C58 C57 10 F / 25V 4 D16 10MQ100N D17 10MQ100N VIN VIN_1 2 3 C54 100nF 1N914 U15 LT1507CS8-3.3 F1 VINplug1 C55 D14 1000m A/30V 22pF / 25V GND J1 SMT6T15CA 1 6 8 100 F / 10V 100 F / 10V C60 3,3nF / 10% 2 jumper_NO D18 10MQ100N D19 10MQ100N I Vddio VDDPLL + + Jack Dia.2.1mm VINplug2 C59 22pF / 25V JP6 1 VDDIO VIN C98 U22 NC NC NC R30 NC 2 C100 1F 14 1 DRV V+ V+ Batt+ 8 FASTCHG PGM3 PGM2 J3 10 9 D28 2 Vbatt+ 15 D25 10MQ100N D26 10MQ100N U16 MAX 713CSE Vbatt+ 5 6 150R C99 10 F / 25V 7 8 10nF Q1 MJD45H11 R77 6R8 1 V- 2 R AT91EB42 Evaluation Board User Guide Timeout 264mn 5 cel. NiCd 1 CB21 2 Vbatt2 V+ 2 5 THI Temp CB23 Batt12 VbattPGM1 PGM0 4 3 1 CB22 1 1 2 3 4 TP1 Test Point Corner 1 TP2 Test Point Corner 2 3 V+ 4 NC Figure 6-8. Power Supply and Battery Charger LM334SM R29 VCC3V3 100R Red LED CB19 1 2 R59 4k7 con. male 43045-0400+43031-0007 MOLEX Rth1 1 16 Vlimit REF PB18 Rth2 7 1 CC R60 TC TP4 Test Point Corner 4 TP3 Test Point Corner 3 GND C101 TLO C102 R58 10K 6 Rth1 R79 R62d R62c 10R 10R R62b R62a 10R 10R 10K Rth2 1F 13 11 2 Vbatt2R5 / 1W 10K CTN 10nF in place only if Therm sensor on Batt. is not use. C103 10nF VDDCORE=3.3V VDDIO 3 JP8 jumper_3P 2 U17 4 Vin C1+ C63 C64 1F C1SHDN/SS LT1503CS8-1.8 GND 7 10 F / 16V C28 C62 1F C2+ 6 Vout 3 2 5 1 VCC1V8 1 VDDCORE I Vddcore VDDCORE=1.8V VCC3V3 C61 1F + Appendix B - Schematics 6-9 Appendix B - Schematics Figure 6-9. Battery Type and Connection Battery : 6V / 300mAH NiCd Wire: gauge 20 AWG 1 J2 con. fem. 43025-0400+43030-0007 MOLEX 1 2 3 4 BT1 6V / 300mAH R61 SAFT : VRE 1/2 AA Ref 139 663 Wire: gauge 20 AWG 2 TC 10K CTN SIEMENS B57861S103F40 Tmax 45C 6-10 AT91EB42 Evaluation Board User Guide VCC3V3 VCC3V3 R34 100k U18 U19 VCC3V3 VCC WP 19 20 NRST NRST 1 2 3 VCC 7 RDY/BUSY RESET WP R51 100K 1 2 A0 A1 R31 100k R32 100k VCC3V3 VCC3V3 CB13 1 NPCSA0 CS CB15 4 5 6 NC NC NC 1 NPCSA0 2 13 2 C67 100nF PB17 SDA 3 4 5 6 7 8 9 NC NC NC NC NC NC NC MOSIA MISOA SPCKA SI SO SCK MOSIA MISOA SPCKA 15 16 14 NC NC NC NC NC NC 18 17 16 15 14 13 C65 100nF CB14 2 GND 9 10 11 12 NC NC NC NC AT45DB321-TC 10 SDA1 SCL1 SDA SCL AT24C512W1-10SC-2.7 VCC3V3 11 12 R40 100k PB16 SCL 1 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC GND 8 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Serial EEPROM memory on PIO Data Flash Memory R63 100k R64 100k U20 6 REFin Vin1 Vin2 CB8 AD7817ARU Vin4 Vin3 10 9 VIN4 VIN3 1 1 VDD 2 CB5 2 1 1 VIN1 VIN2 7 8 CB7 VCC3V3 2 CB6 2 NPCSA1 11 10F / 16V VIN[1..4] C6 R68 1K50 1% Vbatt+ 10pF A/D converter on SPIA R 6 7 750R / 1% R 6 9 750R / 1% Vps C7 10pF R 7 0 4K30 / 1% R71 100k U6C 8 PB20_1 9 1 VCC3V3 74LVC02AD 10 NPB20 CB18 PB20 1 2 U6D 74LVC02AD 1 NPB20 13 NPCSA2_1 7 14 12 11 RD/WR VCC3V3 C89 100nF + AT91EB42 Evaluation Board User Guide NCONVST BUSY NPCSA2_1 R65 5 AGND C104 100nF 1 C90 CB17 2 NPCSA1_1 MOSIA MISOA SPCKA 1 5 2 6 DGND 100k 12 R66 100k U21 CS SI SO SCK VCC HOLD WP GND 8 7 3 4 AT25256W-10SC-2.7 R52 100K R53 100K VCC3V3 C70 100nF CONVST BUSY OTI CS RD / WR SCLK Din Dout RD/WR SPCKA MOSIA MISOA 1 2 3 4 16 15 14 13 VCC3V3 VCC3V3 VCC3V3 VCC3V3 PB19 1 CB2 2 IRQ3 1 CB3 2 Figure 6-10. SPI Memories, I2C Memories and SPI ADC NPCSA2 1 CB4 2 VCC3V3 Serial EEPROM memory on SPIA Appendix B - Schematics 6-11 Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL (408) 441-0311 FAX (408) 487-2600 Atmel U.K., Ltd. Coliseum Business Centre Riverside Way Camberley, Surrey GU15 3YL England TEL (44) 1276-686-677 FAX (44) 1276-686-697 Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Atmel Japan K.K. 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 Atmel Operations Atmel Colorado Springs 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL (719) 576-3300 FAX (719) 540-1759 Zone Industrielle 13106 Rousset Cedex France TEL (33) 4-4253-6000 FAX (33) 4-4253-6001 Europe Atmel Rousset Asia Japan Fax-on-Demand North America: 1-(800) 292-8635 International: 1-(408) 441-0732 literature@atmel.com Web Site BBS http://www.atmel.com 1-(408) 436-4309 (c) Atmel Corporation 2000. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life suppor t devices or systems. ARM, Thumb and ARM Powered are registered trademarks of ARM Limited. ARM7TDMI is a trademark of ARM Ltd. All other marks bearing (R) and/or TM are registered trademarks and trademarks of Atmel Corporation. Terms and product names in this document may be trademarks of others. Printed on recycled paper. 1708A-08/00/0M |
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